Oscillators and Voltage-Controlled Oscillators (VCOs)

Fig 1 — Oscillator feedback model with Barkhausen criteria and phase noise summary (left) and VCO block diagram with varactor tuning and K_VCO characteristic (right)

Oscillator feedback model showing amplifier and resonator blocks, Barkhausen criteria, Leeson phase noise equation alongside VCO block diagram with active device, LC tank, varactor, output buffer, V_tune input and tuning range chart

The Role of Oscillators in RF Systems

Every wireless system that transmits or receives a signal needs a stable, accurate frequency reference. The transmitter must modulate a carrier at a precise frequency; the receiver must have a local oscillator (LO) at a precisely known frequency to down-convert the received signal to baseband. The component that generates this frequency reference is the oscillator — and when that frequency must be electronically tuneable, it is a voltage-controlled oscillator (VCO).

Unlike passive components, an oscillator produces an output signal without any RF input — it converts DC power into a periodic AC signal at a frequency determined by its resonant circuit. In a radio system, the VCO output frequency determines the receive or transmit channel. The purity of that frequency — how close it is to a perfect sinusoid — directly affects the system's ability to reject adjacent channels, demodulate data correctly, and meet regulatory spectral emission masks.

📌 VCO in the PLL Context

In virtually every modern RF system the VCO operates inside a Phase-Locked Loop (PLL). The PLL uses negative feedback to lock the VCO's output frequency to a precise multiple of a stable crystal reference. The VCO provides the frequency agility (wide tuning range); the crystal provides the long-term accuracy and low-frequency stability. This article focuses on the VCO itself; a companion article covers the complete PLL architecture.

Principles of Oscillation

The Feedback Model

An oscillator can be understood as a feedback amplifier in which the feedback is positive and tuned to a specific frequency. The block diagram shows an amplifier with voltage gain A(jω) and a frequency-selective feedback network with transfer function β(jω). The closed-loop gain is:

Closed-loop gain of a feedback amplifier

\frac{V_{out}}{V_{in}} = \frac{A (j ω)}{1 - A (j ω) β (j ω)}

When the denominator approaches zero — i.e., when A(jω)β(jω) → 1∠0° — the closed-loop gain becomes infinite. The circuit can sustain an output with zero external input: it oscillates.

The Barkhausen Criteria

The conditions for sustained, steady-state oscillation at frequency ω₀ are known as the Barkhausen criteria. Both must be satisfied simultaneously at the same frequency:

Barkhausen criteria — magnitude condition

| A (j ω_{0}) \cdot β (j ω_{0}) | = 1

The loop gain magnitude must equal exactly unity. If |Aβ| > 1 the oscillation amplitude grows until nonlinear saturation reduces the effective gain back to 1. If |Aβ| < 1 oscillations die out.

Barkhausen criteria — phase condition

∠ A (j ω_{0}) + ∠ β (j ω_{0}) = 0 ° (or 360°, 720°, …)

The total phase shift around the loop must be 0° (or any integer multiple of 360°). Positive feedback. The frequency-selective resonator sets the frequency at which this phase condition is uniquely met.

In practice, an oscillator is designed with initial loop gain slightly greater than 1 (|Aβ| > 1) to ensure reliable start-up from noise. The amplitude then grows until the transistor enters a nonlinear region (compression), which reduces the effective gain until the steady-state condition |Aβ| = 1 is reached automatically. This self-limiting mechanism sets the oscillation amplitude.

The Negative Resistance Model

An alternative but equivalent view is the negative resistance model. An LC tank circuit has energy losses represented by a parallel resistance R_p (from inductor winding resistance, substrate loss, and radiation). These losses cause oscillations to decay. The active device (transistor) introduces a negative resistance −R_act into the circuit. Sustained oscillation requires:

Negative resistance oscillation condition

| R_{act} | \geq R_{loss}

R_act is the negative resistance presented by the active device (e.g., a cross-coupled transistor pair). R_loss is the total resonator loss resistance. The negative resistance cancels the losses and sustains oscillation. This model is particularly useful for microwave oscillator design.

LC Oscillator Topologies

Colpitts Oscillator

The Colpitts oscillator uses a capacitive voltage divider (C1 and C2 in series) as the feedback network, with an inductor L completing the LC resonant tank. The feedback fraction is β = C1/(C1 + C2), and the resonant frequency is:

Colpitts oscillator resonant frequency

f_{0} = \frac{1}{2 π \sqrt{L C_{eq}}} C_{eq} = \frac{C_{1} C_{2}}{C_{1} + C_{2}}

C_eq is the series combination of C1 and C2. The start-up condition requires transconductance g_m ≥ (C1/C2 + C2/C1 + 2)/R_p where R_p is the equivalent parallel tank resistance.

The Colpitts is widely used in RF ICs because the capacitive divider is easily implemented as MOS capacitors or varactors. The common-source Colpitts (gate as input, source to tank tap) and common-base Colpitts (Clapp variant) are both standard RFIC building blocks.

Hartley Oscillator

The Hartley oscillator is the inductive dual of the Colpitts — the feedback is taken from a tapped inductor (L1 and L2 in series with mutual coupling M) and a single capacitor C completes the tank. The resonant frequency is:

Hartley oscillator resonant frequency

f_{0} = \frac{1}{2 π \sqrt{(L_{1} + L_{2} + 2 M) C}}

M is the mutual inductance between L1 and L2 (positive if wound in the same direction). Hartley oscillators are less common in integrated circuits (tapped inductors are harder to implement on-chip) but widely used in discrete RF designs at HF and VHF frequencies.

Cross-Coupled LC VCO (Differential)

The cross-coupled differential LC VCO is the dominant topology in modern RFIC design. Two transistors (M1 and M2 in CMOS, or Q1 and Q2 in SiGe) are cross-connected: the drain/collector of M1 drives the gate/base of M2, and vice versa. This cross-coupling creates a negative resistance of −2/g_m presented differentially across the LC tank:

Negative resistance of a cross-coupled pair

R_{neg} = - \frac{2}{g_{m}}

For oscillation: 2/g_m ≤ R_p (tank parallel resistance). A larger g_m provides more margin against start-up failure. The differential topology cancels even-order distortion and common-mode supply noise, giving better phase noise performance than single-ended designs.

Key advantages of the cross-coupled LC VCO: differential output (ideal for driving a double-balanced mixer directly), common-mode supply rejection, and the ability to use on-chip spiral inductors with Q of 5–20 at 1–10 GHz. It is the circuit behind the local oscillators in virtually every CMOS Wi-Fi, LTE, and 5G chip.

Crystal Oscillators (XO and TCXO)

A quartz crystal is a piezoelectric resonator with an extremely high Q factor (Q = 10,000–100,000) compared to any on-chip LC tank (Q = 5–20). The crystal has a series resonant frequency f_s and a parallel resonant frequency f_p slightly above it. Between f_s and f_p the crystal presents an inductive reactance, which replaces the inductor in a Colpitts or Pierce oscillator circuit.

The Pierce oscillator is the most widely used crystal oscillator topology in ICs, because it requires only one active device, two capacitors (C1 and C2), and the crystal itself — minimising area and power. Its output frequency is set almost entirely by the crystal — the capacitors shift the frequency by a small amount (pulling):

Crystal oscillator frequency with load capacitance

f_{osc} = f_{s} (1 + \frac{C_{m}}{2 (C_{0} + C_{L})})

C_m is the motional capacitance (very small, ~fF). C_0 is the shunt capacitance of the crystal package (~pF). C_L is the external load capacitance presented by the PCB circuit. Adjusting C_L trims the frequency by tens of ppm — this is the "frequency pulling" used in TCXOs and OCXOs.

A Temperature-Compensated Crystal Oscillator (TCXO) adds a temperature-sensing circuit and varactor to compensate the crystal's natural frequency vs temperature characteristic (typically ±25 ppm over −40 to +85°C uncompensated, reduced to ±0.5 ppm with compensation). An Oven-Controlled Crystal Oscillator (OCXO) keeps the crystal at a constant elevated temperature (typically 70–85°C), achieving ±0.01 ppm stability — used in GPS references and test equipment.

Phase Noise

Definition and Impact

An ideal oscillator produces a single spectral line at exactly f₀. A real oscillator has random fluctuations in both amplitude and phase. The amplitude noise is usually suppressed by the oscillator's amplitude-limiting mechanism, but phase noise — random, short-term phase fluctuations — cannot be filtered and appears as spectral energy spread around the carrier. Phase noise is specified as the single-sideband power in a 1 Hz bandwidth at an offset frequency Δf from the carrier, normalised to the carrier power:

Phase noise definition

L (Δf) = 10 {log}_{10} (\frac{P_{SSB}}{(}) dBc/Hz

Phase noise is always negative (in dBc/Hz) — it is a ratio of sideband power to carrier power. Typical values: −90 dBc/Hz at 1 MHz offset for a CMOS VCO; −130 dBc/Hz at 1 MHz for a high-quality OCXO. Lower (more negative) is better.

Phase noise in a receiver LO causes reciprocal mixing: a strong adjacent-channel interferer mixes with the LO's phase noise skirt and falls on top of the desired channel, raising the noise floor and reducing sensitivity. In a transmitter, phase noise causes spectral regrowth — energy spreads into adjacent channels, violating regulatory emission masks. Phase noise is therefore a fundamental system-level constraint, not just a VCO specification.

Leeson's Equation

The classic model for oscillator phase noise was derived by D. B. Leeson in 1966. Leeson's equation relates the phase noise to the oscillator's key physical parameters:

Leeson's phase noise equation

L (Δf) = 10 {log}_{10} [\frac{2 F k T}{P_{sig}} {(\frac{f_{0}}{2 Q Δf})}^{2} (1 + \frac{f_{1/f}}{| Δf |})]

F = oscillator noise figure (device noise factor). k = Boltzmann's constant. T = temperature (K). P_sig = signal power in the resonator (W). Q = loaded quality factor of the resonator. f₀ = oscillation frequency. Δf = offset from carrier. f_1/f = flicker noise corner frequency of the transistor.

Leeson's equation identifies the key levers for phase noise improvement:

Maximise Q. Phase noise ∝ 1/Q². Doubling Q improves phase noise by 6 dB. This is the single most powerful lever — driving the use of high-Q inductors, BAW/SAW resonators, and crystal references.
Maximise P_sig. Phase noise ∝ 1/P_sig. Doubling the signal power in the tank improves phase noise by 3 dB. Limited by breakdown voltage and DC power budget.
Minimise noise figure F. Lower transistor noise (lower F) improves phase noise directly. This connects oscillator design back to the transistor selection criteria discussed in the LNA series.
Reduce f_1/f (flicker corner). Flicker noise up-converts to phase noise near the carrier (within f_1/f of the oscillation frequency). Low-flicker transistors (SiGe HBT, long-channel CMOS) reduce close-in phase noise.

📌 Phase Noise Slope Regions

The phase noise spectrum has three characteristic regions as a function of offset frequency Δf: a 1/Δf³ (−30 dB/decade) region very close to the carrier, dominated by upconverted 1/f flicker noise; a 1/Δf² (−20 dB/decade) region (the Leeson region) dominated by white thermal noise; and a flat noise floor at large offsets, set by the buffer amplifier noise. The corner between 1/Δf³ and 1/Δf² is the Leeson corner frequency f_L = f₀/(2Q).

Voltage-Controlled Oscillators (VCOs)

VCO Operating Principle

A VCO is an oscillator whose output frequency is a function of an applied control voltage V_tune. By replacing a fixed capacitor in the LC tank with a voltage-dependent capacitor (varactor), the resonant frequency — and therefore the output frequency — becomes tuneable:

VCO output frequency

f_{out} = f_{0} + K_{VCO} \cdot V_{tune}

f₀ is the free-running centre frequency (at V_tune = 0 V or mid-range). K_VCO is the VCO gain (tuning sensitivity) in Hz/V or MHz/V. This linear approximation holds over a limited tuning range; the actual f vs V_tune curve is nonlinear due to the varactor's nonlinear C-V characteristic.

Varactors — The Tuning Element

A varactor (variable capacitor) is a reverse-biased p-n junction diode whose depletion capacitance varies with the applied reverse voltage. As the reverse voltage V_R increases, the depletion region widens and the capacitance decreases:

Varactor capacitance vs reverse voltage

C_{j} (V_{R}) = \frac{C_{j0}}{{(1 + \frac{V_{R}}{V_{bi}})}^{m}}

C_j0 = zero-bias junction capacitance. V_bi = built-in junction potential (≈0.6–0.8 V for Si). m = grading coefficient: m = 0.5 for an abrupt junction, m = 0.33 for a linearly graded junction, m = 2 for a hyperabrupt varactor. Hyperabrupt varactors (m = 2) give a more linear f vs V_tune characteristic.

In CMOS processes, varactors are typically implemented as NMOS or PMOS accumulation-mode capacitors (A-MOS varactors), which offer higher Q than p-n junction varactors at RF frequencies and integrate naturally in a standard CMOS process. The capacitance tuning ratio C_max/C_min is typically 2–4 for a CMOS A-MOS varactor, determining the achievable frequency tuning range.

VCO Gain K_VCO and Tuning Sensitivity

K_VCO (pronounced "K-VCO") is the slope of the f vs V_tune characteristic — the frequency change per unit control voltage:

VCO gain K_VCO

K_{VCO} = \frac{d f_{out}}{d V_{tune}} Hz/V or MHz/V

Typical K_VCO values: 10–100 MHz/V for narrowband RFIC VCOs; 500 MHz/V – 1 GHz/V for wideband SDR VCOs. K_VCO appears directly in the PLL open-loop gain and sets the PLL bandwidth trade-off.

K_VCO is a fundamental PLL design parameter. A higher K_VCO gives a wider frequency tuning range but introduces a critical trade-off: K_VCO directly multiplies any noise on the V_tune control line, converting voltage noise into frequency noise (phase noise). In a PLL, supply noise and digital switching noise on the V_tune line create sidebands on the VCO output at the noise frequency. The resulting spurious tones (reference spurs) must be suppressed by the PLL loop filter. This is why wideband VCOs (high K_VCO) are harder to integrate without spur problems.

Tuning Range

The tuning range TR of a VCO is typically expressed as a percentage of the centre frequency:

VCO tuning range

TR = \frac{f_{\max} - f_{\min}}{f_{0}} \times 100 %

Narrowband PLL VCOs: TR = 5–20%. Wideband fractional-N or SDR VCOs: TR = 30–100%. The tuning range is limited by the varactor's C_max/C_min ratio and the inductor's fixed value. Band-switching (switching discrete capacitor arrays) extends TR to multi-octave coverage.

For very wide tuning ranges, a switched-capacitor bank is added in parallel with the varactor. A binary-weighted array of MOS switches selects coarse frequency bands (covering the required range in steps), while the varactor provides fine frequency adjustment within each band. This architecture — used in virtually all modern fractional-N synthesisers — separates the coarse tuning (low K_VCO, good phase noise) from fine tuning (high K_VCO but small range, acceptable spur level).

Ring Oscillators

A ring oscillator consists of an odd number N of inverting stages (typically 3, 5, or 7) connected in a loop. The total phase shift around the loop is 180° from the odd number of inversions plus 180° from the time delay through the chain — satisfying the Barkhausen phase condition. The oscillation frequency is:

Ring oscillator frequency

f_{0} = \frac{1}{2 N t_{pd}}

N = number of inverting stages. t_pd = propagation delay per stage. Each stage contributes 180°/N of phase shift at f₀. The frequency is tuned by varying t_pd — either by changing the supply voltage or by a current-starved inverter (a MOSFET in series with the inverter supply, controlled by V_tune).

Ring oscillators have several advantages: they require no inductor (saving substantial die area), are easily integrated in digital CMOS processes, have a wide tuning range, and are inherently differential if differential delay cells are used. Their critical disadvantage is much worse phase noise than LC VCOs — typically 20–30 dB worse at the same frequency and power — because they lack a high-Q resonator to stabilise the phase. Ring oscillators are used in clock generation, digital delay-locked loops (DLLs), and on-chip timing references where area and power matter more than spectral purity.

VCO Figure of Merit

Comparing VCOs designed at different frequencies, power levels, and tuning ranges requires a normalised figure of merit. The most widely used is:

VCO figure of merit (FoM)

FoM = L (Δf) - 20 {log}_{10} (\frac{f_{0}}{Δf}) + 10 {log}_{10} (\frac{P_{DC}}{1 mW}) dBc/Hz

L(Δf) = measured phase noise at offset Δf (dBc/Hz). The second term normalises for frequency and offset. The third term accounts for power consumption. Lower FoM is better — a VCO with FoM = −180 dBc/Hz is excellent; −160 dBc/Hz is typical for CMOS LC VCOs.

A variant that also rewards wide tuning range is:

FoM_T — including tuning range

{FoM}_{T} = FoM - 20 {log}_{10} (\frac{TR}{10})

TR = tuning range in percent. A VCO with TR = 20% gets 0 dB adjustment; TR = 40% gets +6 dB bonus (wider is rewarded). FoM_T is preferred for wideband VCOs where TR is a primary specification.

VCO Integration in a Phase-Locked Loop

In nearly every practical RF application, the VCO operates as part of a Phase-Locked Loop (PLL). The PLL forces the VCO output frequency to equal N × f_ref, where f_ref is a crystal reference frequency and N is a programmable integer (or fractional-N) divider value. The loop continuously corrects the VCO frequency by comparing the divided output phase with f_ref and adjusting V_tune through a loop filter.

Fig 2 — Integer-N PLL architecture showing how the VCO is controlled by the feedback loop

The VCO's role in the PLL introduces important design considerations:

Loop bandwidth determines noise filtering. The PLL suppresses VCO phase noise inside the loop bandwidth (where the reference is cleaner) and passes it outside. VCO phase noise at offsets beyond the loop bandwidth passes directly to the output. Optimising loop bandwidth balances reference phase noise vs VCO phase noise.
K_VCO sets loop gain. The open-loop gain of the PLL is proportional to K_VCO × I_CP (charge pump current). A stable loop requires proper phase margin, set by the loop filter zero. Changes in K_VCO (due to VCO nonlinearity) shift the loop gain and can destabilise the PLL.
VCO pushing and pulling. Pushing is the sensitivity of VCO frequency to supply voltage (Hz/V); pulling is the sensitivity to output load impedance changes. Both must be minimised through decoupling and buffering to prevent modulation of the VCO by digital supply noise.

Key VCO Design Parameters

Parameter	Symbol	Typical range	Better is	Key trade-off
Phase noise @ 1 MHz	L(1 MHz)	−100 to −150 dBc/Hz	Lower	Requires higher Q and P_sig
Tuning range	TR	5% – 100%	Wider	Higher K_VCO → more V_tune noise sensitivity
Tuning sensitivity	K_VCO	10 – 1000 MHz/V	Lower (for spur)	Lower K_VCO → narrower TR
Power consumption	P_DC	0.5 – 50 mW	Lower	Lower power reduces P_sig → worse phase noise
Output power	P_out	−10 to +5 dBm	Higher	Higher P_out → more DC power needed
Pushing	K_push	0.1 – 5 MHz/V	Lower	Requires good decoupling, regulator
Pulling	K_pull	< 1 MHz pk–pk	Lower	Requires output buffer and isolation
Figure of merit	FoM	−160 to −190 dBc/Hz	Lower	Balances noise, power, and frequency
Start-up time	t_start	1 – 100 μs	Shorter	Fast start-up needs higher \|Aβ\| margin

Questions & Worked Examples

Work through each problem fully before reading the solution.

01

LC Tank Design for 2.4 GHz Colpitts VCO

Problem: Design the LC tank for a Colpitts VCO at 2.4 GHz. Choose L = 2.5 nH (achievable as an on-chip spiral with Q = 12). Find: (a) the total tank capacitance C_eq required, (b) if C1 = 2C2, find C1 and C2, (c) the tank parallel resistance R_p = Q × ω₀ × L, (d) the minimum transconductance g_m for start-up.

(a) Required C_eq from f₀ = 1/(2π√LC_eq)

C_{eq} = \frac{1}{(^{2 π f_{0}) 2} L} = \frac{1}{(^{2 π \times 2.4 \times 10^{9}) 2} \times 2.5 \times 10^{- 9}} = 1.755 pF

(b) Find C1 and C2 with C1 = 2C2 and C_eq = C1C2/(C1+C2)

C_{eq} = \frac{2 C_{2} \cdot C_{2}}{2 C_{2} + C_{2}} = \frac{2 C_{2}^{2}}{3 C_{2}} = \frac{2 C_{2}}{3} ⟹ C_{2} = \frac{3 \times 1.755}{2} = 2.63 pF C_{1} = 5.26 pF

R_{p} = Q \cdot ω_{0} \cdot L = 12 \times 2 π \times 2.4 \times 10^{9} \times 2.5 \times 10^{- 9} = 12 \times 15.08 = 452 Ω

R_p = 452 Ω represents the total tank loss referred to the parallel LC. The active device must overcome this to sustain oscillation.

(d) Minimum g_m for start-up (Colpitts condition: g_m ≥ (C1/C2 + C2/C1 + 2)/R_p)

g_{m,min} = \frac{C_{1} / C_{2} + C_{2} / C_{1} + 2}{R_{p}} = \frac{2 + 0.5 + 2}{452} = \frac{4.5}{452} = 9.96 mS

For reliable start-up across process, voltage, and temperature corners, design for g_m ≥ 3× g_m,min ≈ 30 mS. This sets the minimum transistor bias current I_DS = g_m/2k' (CMOS) or I_C = g_m/V_T (BJT).

Answer: C_eq = 1.755 pF | C1 = 5.26 pF, C2 = 2.63 pF | R_p = 452 Ω | g_m,min = 9.96 mS

With the ratio C1/C2 = 2, the feedback fraction β = C2/(C1+C2) = 1/3. The feedback voltage at the transistor input is one-third of the tank voltage — a moderate feedback ratio that balances start-up reliability against phase noise. A larger ratio (C1 ≫ C2) gives stronger feedback and easier start-up but transfers more transistor noise into the tank.

02

Phase Noise Estimation Using Leeson's Equation

Problem: The 2.4 GHz VCO from Example 1 has: oscillation power P_sig = 1 mW, loaded Q = 10 (slightly lower than the inductor Q due to varactor losses and transistor loading), device noise figure F = 3 dB (noise factor F = 2), flicker corner f_1/f = 1 MHz. Estimate the phase noise at (a) 100 kHz offset and (b) 1 MHz offset.

Leeson corner frequency f_L = f₀/(2Q)

f_{L} = \frac{f_{0}}{2 Q} = \frac{2.4 \times 10^{9}}{2 \times 10} = 120 MHz

Both 100 kHz and 1 MHz offsets are well inside the Leeson 1/Δf² region (both ≪ 120 MHz), so the (f₀/2QΔf)² term dominates the 1/Δf² shape.

Base thermal noise term: 2FkT/P_sig

\frac{2 F k T}{P_{sig}} = \frac{2 \times 2 \times 1.381 \times 10^{- 23} \times 290}{10^{- 3}} = 1.60 \times 10^{- 17}

(a) Phase noise at Δf = 100 kHz (with flicker correction: 1 + f_1/f/|Δf| = 1 + 10 = 11)

L (100 kHz) = 10 {log}_{10} [1.60 \times 10^{- 17} \times {(\frac{2.4 \times 10^{9}}{2 \times 10 \times 10^{5}})}^{2} \times 11]

Evaluate: (2.4×10⁹ / 2×10⁶)² = (1200)² = 1.44×10⁶

L (100 kHz) = 10 {log}_{10} (1.60 \times 10^{- 17} \times 1.44 \times 10^{6} \times 11) = 10 {log}_{10} (2.534 \times 10^{- 10}) = - 96.0 dBc/Hz

(b) Phase noise at Δf = 1 MHz (flicker correction: 1 + 1 = 2)

L (1 MHz) = 10 {log}_{10} (1.60 \times 10^{- 17} \times 120^{2} \times 2) = 10 {log}_{10} (4.608 \times 10^{- 13}) = - 123.4 dBc/Hz

(f₀/2QΔf)² = (2.4×10⁹ / 2×10×10⁶)² = (120)² = 14,400. Phase noise improves by 20 dB for each decade of offset — the classic 1/Δf² slope.

Answer: L(100 kHz) ≈ −96 dBc/Hz | L(1 MHz) ≈ −123 dBc/Hz

The 27 dB difference between 100 kHz and 1 MHz offsets is exactly the expected 20 dB/decade slope plus ~7 dB extra from the flicker noise term (factor 11 vs factor 2). The 1 MHz phase noise of −123 dBc/Hz is reasonable for a CMOS LC VCO at 2.4 GHz — state-of-the-art designs achieve −125 to −130 dBc/Hz at 1 MHz. To improve further: increase Q (better inductor process, reduce varactor losses), increase P_sig (higher bias current, subject to power budget), and use a transistor with lower f_1/f (longer channel length, lower flicker noise).

03

Varactor and Tuning Range Calculation

Problem: A CMOS VCO uses an A-MOS varactor with C_max = 800 fF and C_min = 300 fF over V_tune = 0–1.8 V. A fixed inductor L = 3.0 nH is in the tank. (a) Find the VCO frequency at V_tune = 0 V and V_tune = 1.8 V. (b) Calculate K_VCO assuming linear tuning. (c) What is the tuning range in percent?

(a) Frequency at V_tune = 0 V (C = C_max = 800 fF)

f_{\min} = \frac{1}{2 π \sqrt{L C_{\max}}} = \frac{1}{2 π \sqrt{3.0 \times 10^{- 9} \times 800 \times 10^{- 15}}} = \frac{1}{2 π \times 1.549 \times 10^{- 12}} = 3.254 GHz

Frequency at V_tune = 1.8 V (C = C_min = 300 fF)

f_{\max} = \frac{1}{2 π \sqrt{3.0 \times 10^{- 9} \times 300 \times 10^{- 15}}} = 5.305 GHz

(b) K_VCO (linear approximation over 0–1.8 V)

K_{VCO} = \frac{f_{\max} - f_{\min}}{V_{\max} - V_{\min}} = \frac{5.305 - 3.254}{1.8} = 1.139 GHz/V = 1139 MHz/V

This is a high K_VCO — appropriate for a wideband SDR application but would cause excessive reference spur sensitivity in a narrowband PLL. In practice a switched-capacitor coarse bank would be added to reduce K_VCO per band to ~200 MHz/V.

TR = \frac{5.305 - 3.254}{4.280} \times 100 = 47.9 %

Answer: f_min = 3.254 GHz, f_max = 5.305 GHz | K_VCO = 1139 MHz/V | TR = 47.9%

A 48% tuning range covering 3.25–5.31 GHz would cover the entire 5G FR1 sub-6 GHz band from a single VCO — a powerful result. The C_max/C_min ratio of 800/300 = 2.67 maps to a frequency ratio of √2.67 = 1.63, consistent with the calculated f_max/f_min = 5.305/3.254 = 1.63. This square-root dependence means that to double the frequency tuning range, the capacitance tuning ratio must quadruple — a key constraint in varactor and tank design.

04

VCO Figure of Merit and Comparison

Problem: Compare the following three VCOs using the standard FoM. Which is the best design?

VCO-A: f₀ = 2.4 GHz, L(1 MHz) = −122 dBc/Hz, P_DC = 5 mW, TR = 15%
VCO-B: f₀ = 5.0 GHz, L(1 MHz) = −118 dBc/Hz, P_DC = 8 mW, TR = 20%
VCO-C: f₀ = 2.4 GHz, L(1 MHz) = −115 dBc/Hz, P_DC = 1.2 mW, TR = 18%

FoM = L(Δf) − 20 log(f₀/Δf) + 10 log(P_DC/1mW)

{FoM}_{A} = - 122 - 20 {log}_{10} (\frac{2.4 \times 10^{9}}{10^{6}}) + 10 {log}_{10} (\frac{5}{1}) = - 122 - 67.6 + 7.0 = - 182.6

{FoM}_{B} = - 118 - 20 {log}_{10} (5000) + 10 {log}_{10} (8) = - 118 - 74.0 + 9.0 = - 183.0

{FoM}_{C} = - 115 - 67.6 + 10 {log}_{10} (1.2) = - 115 - 67.6 + 0.79 = - 181.8

FoM-A = −182.6 | FoM-B = −183.0 | FoM-C = −181.8 → VCO-B is the best design (lowest FoM)

Despite operating at more than twice the frequency and having 7 dB worse phase noise than VCO-A, VCO-B wins the FoM comparison because the frequency normalisation term (20 log f₀/Δf) rewards higher operating frequency by 6.4 dB, and its phase noise is still respectable. VCO-C has excellent power efficiency but its 7 dB worse phase noise — probably a consequence of running at very low P_sig — is not fully compensated by the power savings. This illustrates that the FoM is not simply "lowest phase noise wins" or "lowest power wins"; it rewards balanced designs that achieve low phase noise efficiently relative to frequency.

05

Phase Noise Impact on Adjacent Channel Interference

Problem: A Wi-Fi 802.11ax receiver uses a VCO LO with phase noise L(Δf) = −120 dBc/Hz at 1 MHz offset. An adjacent-channel interferer at 20 MHz offset (one 20 MHz channel away) arrives at the antenna at −30 dBm. The desired signal is at −70 dBm. (a) Calculate the interferer power that reciprocally mixes into the desired channel (1 Hz bandwidth). (b) Estimate the total noise power from reciprocal mixing across the 20 MHz desired channel bandwidth. (c) Does this create a problem?

(a) Phase noise at the channel offset (20 MHz channel spacing → evaluate L at 20 MHz)

L (20 MHz) \approx L (1 MHz) - 20 {log}_{10} (\frac{20}{1}) = - 120 - 26.0 = - 146 dBc/Hz

Using 20 dB/decade roll-off (1/Δf² region). At 20 MHz offset the phase noise is 26 dB better than at 1 MHz.

Mixed interferer power per Hz in desired channel = P_interferer + L(20 MHz)

P_{mix,1Hz} = - 30 + (- 146) = - 176 dBm/Hz

(b) Total reciprocal mixing noise across 20 MHz desired channel

P_{mix,total} = - 176 + 10 {log}_{10} (20 \times 10^{6}) = - 176 + 73.0 = - 103 dBm

N_{thermal} = - 174 + 73 + 6 = - 95 dBm

Reciprocal mixing noise = −103 dBm vs thermal floor = −95 dBm → 8 dB below thermal noise — no problem here

The reciprocal mixing contribution (−103 dBm) is 8 dB below the thermal noise floor (−95 dBm), so it is negligible in this case. However, if the interferer were 8 dB stronger (−22 dBm, which is realistic for a nearby Wi-Fi AP), the reciprocal mixing noise would equal the thermal floor and degrade the receiver noise figure by 3 dB. IEEE 802.11ax requires the receiver to tolerate a −30 dBm adjacent channel interferer with < 3 dB desensitisation — with L(1 MHz) = −120 dBc/Hz this is just met. A VCO with L(1 MHz) = −110 dBc/Hz would fail this test, illustrating directly how phase noise specification flows from the system's interference scenario.